This is a circuit for converting parallel binary bits per clock cycle into serial bits per clock cycle, and more specifically is a circuit comprising a digital phase locked loop, counters, registers and a multiplexer for accomplishing this conversion.
There is a common need in the industry for the conversion of parallel to serial data streams. For example, it is common for an image generating circuit to process image data in the form of a number of bits per word in parallel, but to convert this image data into serial bits for printing on a raster output scanner (ROS). To use a numerical example, if the image data words are eight bits, then these words could be loaded in parallel into an eight bit register by using a system clock, and clocked out serially to the ROS using a clock with a frequency eight times higher than the system clock. The higher frequency clock can be produced using a phase lock loop. The main problem with this system is that the higher frequency clock may be difficult to produce and control since special high-frequency components may be required in the circuit. Current methods of meeting this requirement usually rely on analog techniques and multiplication of the original clock to higher frequencies which require very selective discrete components and very careful layout and electromagnetic emissions protections. One particular device (Model AD9560 Pulse Width Modulator from Analog Devices) has the limitation that only certain high addressability codes are allowed. A method of converting parallel data to serial data without the use of a higher frequency clock is needed.